TI C2000 CLA Software Development Guide

CLA Overview

CLA (Control Law Accelerator) is a 32-bit floating-point programmable hardware accelerator built into the C2000 MCU, designed specifically for high real-time control algorithms.

Core value: Running in parallel with C28x CPU, doubling equivalent computing power

Direct access to peripherals: ePWM/HRPWM, ADC, eCAP, eQEP, GPIO, SPI, etc

Advantages: Reduce interrupt latency, shorten control loop cycle, and alleviate CPU load

Introduction to Development

development tools

Main IDE: Code Composer Studio (CCS)

Compiler: C2000 code generation tool, supports CLA C language compilation

Support: MATLAB Embedded Coder automatically generates CLA code

Development steps

Learn the official CLA training manual

Run C2000Ware samples (CLAmath, driverlib)

Refer to FAQ and Debugging Tips

Reference digital power supply and other system use cases

Example Resources

Basic Mathematics Library: CLAmath Library

Device drivers: driverlib, Device_Support

Reference Design: PFC, Digital Power SDK

CLA type and device differences

CLA is divided into 3 generations, corresponding to different devices and functions:

CLA type core characteristics represent chips

Type 0 Basic Edition, Program Space 12 Bit (4KW) F2803x, F2805x, F2806x

Type 1 16 bit address space (64KW), task interruptible CPU F2807x, F2837xD/S

Type 2 supports background tasks, hardware breakpoint enhancement F28004x, F2838xD/S

Core FAQ (Key Information)

Independence: CLA has independent buses, registers, and pipelines, which can run independently without the CPU after configuration

Programmable: Fully programmable, supports C language/assembly, no fixed algorithms

data sharing

Channel: Shared RAM+Message RAM

Rule: Shared variables must be defined on the C28x end, CLA read-only/write

Message RAM: CPU → CLA (CPU write, CLA read); CLA → CPU (CLA write, CPU read)

Differences in data types

Int: CLA=32 bits, C28x=16 bits

Pointer: CLA=16 bits, C28x=32 bits, need to be aligned with CLA-FPTR consortium

task trigger

Source: Peripheral interrupts, software triggers, inter task triggers, background tasks (Type 2)

Configuration: old device MPIRCRSEL1, new device CLA1TASKSRCSELx

Task execution

Nesting is not supported (Type2 backend tasks support level 1 preemption)

End instruction: MSTOP

Program space: Type0=4096 words, Type1 and above=64K words

Interruption and synchronization

CLA can send interrupts to C28x: task completion, software forcing, floating point overflow

Resource Access: Hardware auto arbitration to avoid writing to the same register simultaneously

Mission terminated

Not running: MICLR clearing flag

Running: MCTL soft reset terminated

Debugging skills

Debugging environment

CCS simultaneously debugs C28x and CLA, sharing JTAG

Breakpoint: __mdebugsstop() built-in breakpoint instruction

Common Faults

Task not started: Check trigger source, initialization sequence, interrupt enable

Software trigger failure: Check MCTL, MIER, IACK parameters

Variable not updated:. cratchpad/. bs_cla not allocated to RAM

Task timing

Method 1: Read ePWM timer count

Method 2: Flip GPIO and measure with oscilloscope

Comparison between CLA and C28x+FPU Core

Project CLA C28x+FPU

Execution mode independent parallel main CPU internal

4 floating point registers (MR0-MR3) and 8 registers (R0H-R7H)

Floating point operation, single cycle execution, 2-cycle pipeline

Pipeline independent 8-stage and fixed-point sharing

Two full mode support for addressing modes

Interrupt Nesting None (Type2 supports level 1) Supports Nesting

Memory access limited to CLA program/data/message RAM, full device memory

Single step mode, single cycle step refresh pipeline

Key issues

Question 1: How do CLA and C28x CPUs securely share data? What are the pitfalls?

Answer: Interact through shared RAM and dedicated message RAM; Shared variables must be defined on the C28x end and use a fixed width type of std int. h (such as uint322-t). The biggest pitfall is the incompatibility between int and pointer length: CLA’s int is 32-bit and the pointer is 16 bit, while C28x is the opposite. The structure pointer must be aligned with a 32-bit union, otherwise addressing errors occur.

Question 2: What are the triggering methods and execution rules for CLA tasks? What is the maximum program space?

Answer: Supports four types of triggers: external interrupt, software IACK, inter task, and background task (Type 2); Execute only one task at a time without nesting (Type2 backend can be preempted). Program space: Type0 is 4KW (approximately 2000 instructions), Type1 and above are 64KW, and tasks end with MSTOP instructions.

Question 3: What are the core advantages and limitations of CLA in control algorithms compared to C28x+FPU?

Answer: The advantages include independent parallel operations, single cycle floating-point multiplication/conversion, direct access to peripherals, lower control latency, and suitability for fast inner loop control. The limitations include fewer floating-point registers (4), simple addressing mode, no loop instructions, limited memory access, making it more suitable for lightweight real-time algorithms and not suitable for complex logic and large computational tasks.